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PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
PD161661
POWER SUPPLY FOR TFT-LCD DRIVER
DESCRIPTION
The PD161661 is a power supply IC for TFT-LCD driver. This ICs can generate the levels which TFT-LCD driver need, from single voltage input.
FEATURES
* To generate 3 levels from single voltage input * To integrate regulator circuit for source driver
ORDERING INFORMATION
Part number Package Chip/Wafer
PD161661P/W
Remark
Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative.
The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S15917EJ1V0PM00 (1st edition) Date Published January 2002 NS CP(K) Printed in Japan
(c)
2002
PD161661
1. BLOCK DIAGRAM/SYSTEM DIAGRAM
VDC VSS DCON CR Oscillator
C1+ C1- C2+ C2- C3+
DC/DC Converter Contorl
FS LFS LPM Divider
DC/DC Converter
C3- C4+ C4- C5+
RGONP EXRVS RSEL
VDC x3 Regulator Control RC1 RC2
VDC x6
C5-
VO
0 V (VSS)
VREG VREFSEL
VREF VDD1 VDD2
VREF VS MVS RC1 ACS LACS RC1
VEE
TESTIN1TESTIN3 TESTOUT RC2
Remark /xxx indicates active low signal.
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Preliminary Product Information S15917EJ1V0PM
PD161661
2. PIN CONFIGURATION (Pad Layout)
Chip size: X = 3.60 mm, Y = 3.40 mm Pad size : 100 x 100 m TYP. (1) Alignment mark T.B.D.
2
(2) Arrangement
DUMMY DUMMY
C5+
C4+
C3+
C2+
C1+
C5-
C4-
C3-
C2-
24 DUMMY VDD1 DUMMY VO DUMMY Y DUMMY X DUMMY TESTIN1 TESTIN2 TESTIN3 TESTOUT DUMMY 36 37 D161661 25 Chip Surface (Bump size)
C1-
13 12 DUMMY VDC VSS VDD2 VS MVS DUMMY DUMMY DCON RGONP LPM 1 48 DUMMY
DUMMY
DUMMY
Remark T.B.D. : To be determined.
VREFSEL
DUMMY
EXRVS
VSS
LACS
ACS
VREF
RSEL
LFS
FS
Preliminary Product Information S15917EJ1V0PM
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PD161661
Table 2-1. Pad Layout
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pad name DUMMY LPM RGONP DCON DUMMY DUMMY MVS VS VDD2 VSS VDC DUMMY DUMMY C1 C1
- + -
X[mm] 1632 1632 1632 1632 1632 1632 1632 1632 1632 1632 1632 1632 1237.5 1012.5 787.5 562.5 337.5 112.5 -112.5 -337.5 -562.5 -787.5 -1012.5 -1237.5 -1632 -1632 -1632 -1632 -1632 -1632 -1632 -1632 -1632 -1632 -1632 -1632
Y[mm] -1237.5 -1012.5 -787.5 -562.5 -337.5 -112.5 112.5 337.5 562.5 787.5 1012.5 1237.5 1532 1532 1532 1532 1532 1532 1532 1532 1532 1532 1532 1532 1237.5 1012.5 787.5 562.5 337.5 112.5 -112.5 -337.5 -562.5 -787.5 -1012.5 -1237.5
Pad No. 37 38 39 40 41 42 43 44 45 46 47 48
Pad name DUMMY EXRVS LFS FS RSEL ACS VREFSEL LACS VSS VREF DUMMY DUMMY
X[mm] -1237.5 -1012.5 -787.5 -562.5 -337.5 -112.5 112.5 337.5 562.5 787.5 1012.5 1237.5
Y[mm] -1532 -1532 -1532 -1532 -1532 -1532 -1532 -1532 -1532 -1532 -1532 -1532
C2 C2
+ -
C3 C3
+
C4- C4
+ -
C5 C5
+
DUMMY DUMMY VDD1 DUMMY VO DUMMY DUMMY DUMMY TESTIN1 TESTIN2 TESTIN3 TESTOUT DUMMY
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Preliminary Product Information S15917EJ1V0PM
PD161661
3. PIN FUNCTIONS
(1/2)
Symbol VDC VSS VDD1 Pin Name Power supply Ground DC/DC converter output Pad No. 11 10, 45 26 I/O - - - Description Power supply for logic circuit and DC/DC converter. Ground for logic circuit and DC/DC converter power supply. x6 voltage boost output of DC/DC converter. Outputs a potential that is VDC boosted to six times the original level. Use this pin connected to a voltage stabilization capacitor. VDD2 DC/DC converter output 9 - x3 voltage boost output of DC/DC converter. Outputs a potential that is VDC boosted to three times the original level. Use this pin connected to a voltage stabilization capacitor. VO Rectangle signal output for negative boost 28 - Rectangle signal output for negative boost. A potential that is VDC boosted to five times the original level is used for the VO voltage range. A negative power supply can be created for gate IC bottom output by connecting an external component to this pin. VS VREF Regulator output Reference voltage input/output 8 46 - I/O Regulator output for source driver. Use this pin connected to a voltage stabilization capacitor. Reference voltage input/output of VS regulator. The internal reference supply voltage is used when VREFSEL = L. At this time, this pin can also be used as the reference voltage output of the negative power supply regulator incorporated in the gate driver, etc. When VREFSEL = H, the external reference voltage can be input as the regulator reference voltage. DCON DC/DC converter control 4 I DC/DC converter ON/OFF control. Use this pin connected to DC/DC converter control pin (DCON) of source driver or the control port output of CPU. DCON = H : DC/DC converter ON DCON = L : DC/DC converter OFF RGONP Regulator control 3 I Regulator ON/OFF control for source driver voltage (VS). Use this pin connected to the regulator control pin (RGONP) of the source driver or the control port output of CPU. RGONP = H : Regulator ON RGONP = L : Regulator OFF EXRVS VS regulating resistor selection 38 I This pin selects whether to use the internal feedback resistor or connect an external resistor for the VS regulator amplifier. When external resistor connection is selected, configure a feedback circuit between the MVS, VS, and VSS pins by connecting an external resistor. EXRVS = H: External resistor connection EXRVS = L: Internal feedback resistor used.
Preliminary Product Information S15917EJ1V0PM
5
PD161661
(2/2)
Symbol MVS Pin Name VS regulator input Pad No. 7 I/O - Description Feedback input (+) of the regulator amplifier for VS output. This pin is used as follows according to the setting of EXRVS. EXRVS = H : To connect external resistor. EXRVS = L : Leave it open. RSEL Internal resistor selection for regulator 41 I This pin selects the internal resistor for the regulator and sets the source driver supply voltage output from the VS pin as follows. Note that this pin setting is valid when EXRVS = L. RSEL = H: 5.0 V VS output voltage RSEL = L: 4.0 V VS output voltage VREFSEL Regulator reference voltage input selection 43 I This pin selects external or internal reference voltage of VS regulator. When external reference is selected, input reference voltage from VREF pin. VREFSEL = H : External reference voltage is selected. VREFSEL = L : Internal reference voltage is selected. LPM Low power mode signal 2 I Control signal for low power mode. LPM = H : Low power mode LPM = L : Normal mode The settings made by the LACS and LFS pins are valid in the low power mode, and settings made by the ACS and FS pins are valid in the normal mode. Connect to low power mode setting pin (LPMP) of source driver or control port output of CPU. ACS LACS Amp current selection Amp current selection 42 44 I I To select Amp current in normal mode. For detail, refer to 4. MODE DESCRIPTION. To select Amp current in low power mode. For detail, refer to 4. MODE DESCRIPTION. FS OSC frequency selection 40 I To select OSC frequency for DC/DC converter when in normal mode. For detail, refer to 4. MODE DESCRIPTION. LFS Low power mode OSC frequency selection C1 , C1 C2 , C2 C3 , C3 C4 , C4 C5 , C5
+ + + + + - - - - -
39
I
To select OSC frequency for DC/DC converter in low power mode. For detail, refer to 4. MODE DESCRIPTION.
Capacitor connect pin for boost
15, 14 17, 16 19, 18 21, 20 23, 22
-
Capacitor connect pin for boost of DC/DC converter. Connect these pins between each Cn and Cn . The capacitance and tolerance of each capacitor are shown below. Capacitance : 1 F Tolerance : 10 V
+ -
TESTIN1 to TESTIN3 TESTOUT DUMMY
Test TEST output Dummy pin
32 to 34 35 1, 5, 6, 12, 13, 24, 25, 27, 29 to 31, 36, 37, 47, 48
I O -
IC test mode pin. Normally, leave it open. IC test mode pin. Normally, leave it open. Dummy pin. Leave it open.
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Preliminary Product Information S15917EJ1V0PM
PD161661
4. MODE DESCRIPTION
DC/DC converter control
DCON H L DC/DC converter ON DC/DC converter OFF
Regulator control
RGONP H L Regulator ON Regulator OFF (VS output : High impedance)
VS regulating resistor
EXRVS H L External resistor Internal resistor
Regulator reference voltage input selection
VREFSEL H L VREF : External reference voltage input VREF : Internal reference voltage output
VS regulator selection
VS RSEL H L 5.0 V 4.0 V
Amp current selection
ACS, LACS
Note
VS Source current Sink current 0.5 A 5 A Amp current 1 A 10 A
H L
3 mA > 3 mA >
Note
ACS LACS
: Selection of current during normal driving : Selection of current in low power mode
OSC frequency selection
FS, LFS
Note
OSC fOSC/8 fOSC/2
H L
Note
FS
: Selection of current during normal driving
LFS : Selection of current in low power mode
Preliminary Product Information S15917EJ1V0PM
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PD161661
Low power mode selection
LPM H Low power mode The settings made by LACS and LFS are valid. L Normal mode The settings made by AC and FS are valid. Drive mode
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Preliminary Product Information S15917EJ1V0PM
PD161661
Figure 4-1. Example of Internal/External resistor for the regulator
VREG VREFSEL
VREF
VREF MVS
VS

VREG VREFSEL
VREF
VREF MVS Rb VS Ra
VS
Remark VS = (1+Rb/Ra) VREF
Preliminary Product Information S15917EJ1V0PM
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PD161661
5. POWER ON/OFF SEQUENCE
5.1 Power ON Sequence T.B.D.
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Preliminary Product Information S15917EJ1V0PM
PD161661
5.2 Power OFF Sequence T.B.D.
Preliminary Product Information S15917EJ1V0PM
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PD161661
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Supply Voltage Input Voltage Input Current Output Voltage Output Current Storage Temperature VI II VDD1 IO Tstg Symbol VDC Rating -0.5 to + 6.0 -0.5 to VDC + 0.5 10 -0.5 to +38 10 -30 to +85 -55 to +125 Unit V V mA V mA C C
Operating Ambient Temperature TA
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = -30 to +85C, VSS = 0 V)
Parameter Supply Voltage Input Voltage VI Symbol VDC Condition MIN. 2.50 0 TYP. 2.85 MAX. 3.60 VDC Unit V V
Electrical Characteristics (Unless otherwise specified, TA = -30 to +85C, VDC = 2.5 to 3.6 V, VSS = 0 V)
Parameter High Level Input Voltage Low Level Output Voltage Boost Voltage Symbol VIH VIL VDD1 ACS (LACS) = H, FS (LFS) = L, IDD1 = 100 A Boost Voltage VDD1 ACS (LACS) = H, FS (LFS) = H, IDD1 = 100 A Output Voltage VS1 Rsel = H, FS (LFS) = L, IS = 3.0 mA Output Voltage VS2 Rsel = L, FS (LFS) = L, IS = 3.0 mA VDC Static Current Consumption VDC1 ACS (LACS) = H, FS (LFS) = L, IDD1 = IS = 0.0 mA VDC Static Current Consumption Ivdcd ACS (LACS) = H, FS (LFS) = L, IDD1 = IS = 0.0 mA VREF Voltage 2.25 2.50 2.75 V T.B.D. T.B.D. 3.5 4 4.5 V 4.5 5 5.5 V 5 VDC 6 VDC V 5 VDC Condition MIN. 0.7 VDC 0.3 VDC 6 VDC TYP. MAX. Unit V V V
A A
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Preliminary Product Information S15917EJ1V0PM
PD161661
[MEMO]
Preliminary Product Information S15917EJ1V0PM
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PD161661
[MEMO]
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Preliminary Product Information S15917EJ1V0PM
PD161661
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Preliminary Product Information S15917EJ1V0PM
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